We have seen in the last two years a lot of interesting moves in the CPU market. First we have seen the incredible market increase of the AMD Athlon and the even more incredible Intel inability to regain the market. Intel succeeded to impress also but by failures and CPU problems. It's not a secret that Intel was surprised by Athlon. In fact when AMD attacked with their new CPU line most Intel engineers were working at the Pentium4 and IA64 processor and only a small part of the team was dedicated to Pentium III development. The monopol gives a certain self confidence hard to compete against. Intel was aware that the old Pentium architecture was not able to support many improvements but they probably hoped that they will be able to introduce the Pentium 4 in time and to crash the AMD expansion.
Pentium 4 was presented late in 2000 but no one can say that it was very successful; it was regarded like a technical curiosity. Indeed Intel made several important architectural changes but the processor's performance in benchmarks was below any expectations. Intel's marketing team went for something known to produce results in computing world: the future. They recognized the weak CPU results in benchmarks but they motivated these results with the fact that Pentium 4 is a CPU for the future and further compilers will take advantage of its potential. Until now Intel seemed to respect its word: 2.0 Ghz parts will be introduced soon which means that in terms of clock speed Intel still has the fastest x86 on the planet. Today we will review a motherboard for Intel Pentium 4 from Epox, but first I'll introduce you the Pentium 4 architecture.

Pentium 4 is based on NetBurst architecture which consists of Hyper Pipelined Technology, Rapid Execution Engine, Execution Trace Cache and a 400MHz system bus. In addition to these Intel brings four other improvements over Pentium architecture which are Advanced Dynamic Execution, Advanced Transfer Cache, Enhanced Floating Point & Multimedia Unit, and Streaming SIMD Extensions 2. I will try to detail a little bit the arhitecture.

Hyper Pipelined Technology

The Hyper Pipelined Technology is advertised by Intel in all its datasheets as the base technology of the NetBurst architecture. The Hyper Pipelined technology is not based on revolutionary things but it's a different approach to optimization and clock speeds. Until now it was just a way to increase a CPU clock: a die shrink. Unfortunately a die shrink implies expensive manufacturing process and it's not always possible (just take a look to Pentium 3).
The Hyper Pipelined Technology is a deeper pipeline which allows several parts of the CPU to run at different speeds than others. The pipeline of the NetBurst architecture consists of three sections: the in-order front end, the out-of order superscalar execution core and the in order retirement unit. The front end decodes and fetches IA32 program instructions and translates them into uops, these uops go into the original program order into the execution core. The execution core optimizes the execution of the uops based on available data and pushes them to the retirement unit which reassembles the uops into the original program order. The older P6 architecture used a ten stages pipeline while the Pentium 4 uses a twenty stages pipeline. This pipeline allows further clock increases but introduces a high degree of uncertainty in many operations. Advanced CPUs use the Branch Prediction technique to predict further instructions and to deliver the current instruction as fast as possible. Unfortunately the prediction algorithms are not deterministic and it's quite possible for an instruction to start again from the beginning of the pipe. And considering the fact that there is a huge difference between a ten and a twenty stage pipeline…
Intel worked to optimize the function of the Pipeline: the front end unit uses a Trace cache which holds the decoded IA32 instructions. This cache increases the response in case of a mis-prediction and it's able to pump to the core as many as 3uops per clock.

Take a look below to the NetBurst architecture diagram:

The diagram is pretty basic and I'll try to give further details about the hidden parts.